1. Field of the Invention
The present invention relates to electronic circuits, and more particularly relates to an on-chip decoupling capacitor.
2. Background Information
Electronic circuits, and particularly computer and instrumentation circuits, have in recent years become increasingly powerful and fast. As circuit frequencies exceed several hundred megahertz (MHz), with the associated spectral components exceeding 10 gigahertz (GHz), noise in the DC power and ground lines increasingly becomes a problem. This noise can arise due to, for example, inductive and capacitive parasitics, as is well known. To reduce this noise, capacitors known as decoupling capacitors are often used to provide a stable supply of power to the circuitry. The decoupling capacitors are placed as close to the load as practical to increase their effectiveness. Typically the decoupling capacitors are placed in the same package as the chip, but unfortunately, this arrangement is costly to manufacture. Typically, one or more capacitors having a low capacitance value are needed to reduce the effect of high frequency, low amplitude noise, while one or more capacitors having a high capacitance value are needed to reduce low frequency, high amplitude noise.
As mentioned above, the closer the capacitor is to the load, the more effective it is in eliminating or reducing the noise in the power and ground lines. Because the integrated circuit on a chip may constitute the load, the most effective solution would be to fabricate a capacitor directly on the chip itself. However, such a capacitor would be costly to manufacture using prior art methodologies. In particular, a typical processing sequence would require a deposition, patterning, and etch of a first dielectric layer, to isolate underlying metal layers from the capacitor. Following the first dielectric layer, the lower plate of the capacitor could be formed by depositing, patterning and etching a first metal layer. Then, the interplate dielectric could be formed by depositing, patterning and etching a second dielectric layer. Next, a second metal layer forming the second plate of the capacitor could be deposited, patterned and etched followed by a final dielectric layer deposition, patterning and etch to isolate the capacitor. The various patterning and etch steps are needed in order to connect one plate of the capacitor to power and the other to ground, as well as to provide vias for interconnection from one or more metal layers below the capacitor to one or more metal layers above the capacitor. Unfortunately, the above described processing requires at least four patterning steps, which is very costly.
What is needed is a manufacturable method and structure for producing a decoupling capacitor directly on the substrate containing the circuitry to which the power is supplied.